Design and metrological validation of a programmable high-voltage I–V measurement system for dielectric breakdown kinetics
Abstract
Accurately distinguishing between intrinsic dielectric breakdown and instrument-induced compliance artifacts is a fundamental requirement in semiconductor reliability metrology. To address this requirement, this paper presents the design and metrological validation of a programmable high-voltage (HV) I–V measurement system for dielectric breakdown kinetics. The architecture integrates a ramp-controlled HV source with a dual-channel, galvanically isolated data acquisition module, achieving an effective post-processed noise floor in the sub-nA range, thereby preserving signal integrity across a wide dynamic range. A central contribution is a compliance-aware extraction strategy. By localizing the intrinsic hard breakdown (HBD) onset at the global maximum of |dI/dV| and explicitly excluding the subsequent compliance-limited region (CLR), this approach removes a major source of ambiguity in breakdown-parameter reporting. Experimental verification on 150 nm Si/SiO2 MOS capacitors demonstrates the system's capability to resolve field-dependent leakage, supporting Fowler–Nordheim and Poole–Frenkel consistency checks with high linearity (R^2>0.97) within a 2–7 MV/cm diagnosti c window. The extracted breakdown field has a mean value of 6.38 MV/cm with a coefficient of variation of 15.7% (n=6), supporting the platform as a transparent and reproducible tool for rigorous dielectric integrity studies and failure analysis.