Design current controller base on FPGA
Abstract
In closed - loop control systems for motors, a current controller is usually designed as the inner loop while the outers are the speed and the position controllers. Therefore, the current controller usually does not need boundary conditions. Most of these controllers are currently operated on software, resulting in lots of computational volumes, complex algorithms and slow responses. To overcome these drawbacks, the current controller should be hardened to increase the responsiveness and reduce the load on the CPU. The goal of this paper is to present the allowance of FPGA technology for users to design hardening of the flow controller regardless of the CPU scan cycles. Experimental and simulation results show that the design of current controllers based on FPGA response meets the response requirements.